Hyper Graph and Coprocessor Design for Vlsi Partitioning Problems

VLSI Cell partitioning is considered as Hypergraph model, which can be a treated a randomized algorithm through the markov chain. This approach helps to give a probabilistic algorithm through transition probability matrices of a markov chain for VLSI partitioning. In the second model SAT problem situation is used to model FPGA Layout. As almost all problems posed in VLSI design and analysis are NPComplete, any attempt to solve them is to identify some reduction tool to NP-Complete problems. One such reduction is attempted through SAT Problem. .